Field-programmable gate arrays (FPGAs) are reprogrammable silicon chips. Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing. In the past, FPGA technology was available to only engineers with a deep understanding of digital hardware design. The rise of high-level system design tools, changes the rules of FPGA programming, delivering new technologies that convert graphical block diagrams into digital hardware circuitry.

Due to their programmable nature, FPGAs are an ideal fit for many different markets. The industry leaders, Xilinx provides comprehensive solutions consisting of FPGA devices, advanced software, and configurable, ready-to-use IP cores. Altera FPGAs offer a wide variety of  configurable embedded SRAM, high-speed transceivers, high-speed I/Os, logic blocks, and routing. These are ideals for markets and applications such as Aerospace & Defense, ASIC Prototyping, Automotive, Broadcasting, Security, Audio, Video, Image Processing, Data centre, Wired/Wireless communication.

Our latest FPGA based IEEE projects are listed below

2015 IEEE Transactions 

  • Fault Tolerant Parallel Filters Based on Error Correction Codes
  • Fully Reused VLSI Architecture of FM0_Manchester Encoding Using SOLS
  • Fast Sign Detection Algorithm for the RNS Moduli Set
  • Partially Parallel Encoder Architecture for Long Polar Codes
  • Low-Power Programmable PRPG With Test Compression Capabilities
  • Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications
  • A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes
  • Arithmetic-Based Binary-to-RNS Converter
  • High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations
  • A Synergetic Use of Bloom Filters for Error Detection and Correction
  • An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis
  • An Accuracy-Adjustment Fixed-Width Booth Multiplier

 

VLSI IEEE Projects 2015 2016 Kerala Thrissur Ernakulam        FPGA Kits Kerala IEEE VLSI Project Centre

Share on FacebookShare on Google+Tweet about this on TwitterEmail this to someoneShare on LinkedIn